Digital signal processors (DSPs) are finding increasingly expanding practical applications in converting supplied analog signals into digital versions and further converting the resultant digital signals back into analog ones after the processing of the digital signals is complete. Such practical applications of digital signal processors include the processing of signals in high-speed modem circuitries for communication systems and equipment, compression of data for the analysis and synthesis of sound information using linear prediction coding technologies, analysis of signal waveforms in sound recognition systems, execution of fast Fourier transform algorithms generation and modification of signals required for various computer-aided operation control systems, and processing of data for use n computer graphics technologies.
Among these various practical applications of digital signal processing technologies, those using the fast Fourier transform algorithms outweigh other applications. One of the important demands in using the fast Fourier transform algorithms is to effectively reduce the number of addressing cycles required for the execution of the programs to carry out the algorithms. A prime object of the present invention is to meet such a demand.